In non-volatile memory devices it is desirable to increase the ratio of a first capacitance, which is between a control gate and a floating gate, to a second capacitance, which is between a floating gate and a substrate. The ratio between the first and second capacitances is known as the gate coupling ratio. By having a high gate coupling ratio smaller peripheries can be used, thus desirably saving chip space.
One way to increase the gate coupling ratio is to enlarge the width of the floating gates in a non-volatile memory. However, increasing the width of the floating gates undesirably increases the size of the non-volatile memory device. In addition, as the width of the floating gates increases spaces between floating gates decreases. The floating gates are typically formed by depositing a conformal layer and then etching the layer to form the floating gates. If the spaces between the floating gates are too small, sub-lithographic processes are used to remove any unwanted portions of the layer to form the spaces. Sub-lithographic processes are expensive and difficult to control in a manufacturing environment. Therefore, a need exists for a manufacturable process to decrease the floating gates size without significantly decreasing the gate coupling ratio.
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